LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 21

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
3.4.1 Reset Source Identification Register (RSID - 0x400F C180)
This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources are
described below.
Table 8.
Bit
0
1
2
3
31:4 -
Symbol Description
POR
EXTR
WDTR
BODR
Reset Source Identification register (RSID - address 0x400F C180) bit description
Assertion of the POR signal sets this bit, and clears all of the other bits in
this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
Assertion of the RESET signal sets this bit. This bit is cleared only by
software or POR.
This bit is set when the Watchdog Timer times out and the WDTRESET bit
in the Watchdog Mode Register is 1. This bit is cleared only by software or
POR.
This bit is set when the V
BOD reset trip level (typically 1.85 V under nominal room temperature
conditions).
If the V
the BOD reset trip level and recovers, the BODR bit will be set to 1.
If the V
the BOD reset trip level and continues to decline to the level at which POR
is asserted (nominally 1 V), the BODR bit is cleared.
If the V
above the BOD reset trip level, the BODR will be set to 1.
This bit is cleared only by software or POR.
Note: Only in the case where a reset occurs and the POR = 0, the BODR
bit indicates if the V
or not.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
DD(REG)(3V3)
DD(REG)(3V3)
DD(REG)(3V3)
Rev. 2 — 19 August 2010
voltage dips from the normal operating range to below
voltage dips from the normal operating range to below
voltage rises continuously from below 1 V to a level
DD(REG)(3V3)
DD(REG)(3V3)
voltage was below the BOD reset trip level
voltage reaches a level below the
Chapter 3: LPC17xx System control
UM10360
© NXP B.V. 2010. All rights reserved.
21 of 840
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NA
Reset
value
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