LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 763

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.2.6 Interrupt Active Bit Registers
34.4.2.7 Interrupt Priority Registers
Table 649. ICPR bit assignments
Remark: Writing 1 to an ICPR bit does not affect the active state of the corresponding
interrupt.
The IABR0-IABR3 registers indicate which interrupts are active. See:
The bit assignments are shown in
Table 650. IABR bit assignments
A bit reads as one if the status of the corresponding interrupt is active or active and
pending.
The IPR0-IPR27 registers provide a 5-bit priority field for each interrupt. These registers
are byte-accessible. See the register summary in
register holds four priority fields, that map to four elements in the CMSIS interrupt priority
array IP[0] to IP[111], as shown:
Bits
[31:0]
Bits
[31:0]
•
•
the register summary in
Table 645
IPR27
IPRm
IPR0
.
.
.
.
.
.
for which interrupts are controlled by each register.
Name
CLRPEND
Name
ACTIVE
31
All information provided in this document is subject to legal disclaimers.
IP[4m+3]
IP[111]
IP[3]
Rev. 2 — 19 August 2010
Table 644
24
23
Function
Interrupt clear-pending bits.
Write:
0 = no effect
1 = removes pending state an interrupt.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
Function
Interrupt active flags:
0 = interrupt not active
1 = interrupt active.
Table
IP[4m+2]
IP[110]
IP[2]
for the register attributes
650.
Chapter 34: Appendix: Cortex-M3 user guide
16
.
.
.
.
.
.
15
Table 644
IP[4m+1]
IP[109]
IP[1]
for their attributes. Each
8
7
UM10360
IP[108]
IP[4m]
© NXP B.V. 2010. All rights reserved.
IP[0]
0
763 of 840