LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 584

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 540. D/A Control register (DACCTRL - address 0x4008 C004) bit description
Table 541: D/A Converter register (DACR - address 0x4008 C008) bit description
30.5 Operation
UM10360
User manual
Bit
0
1
2
3
31:4
Bit
15:0
Symbol
INT_DMA_REQ 0
DBLBUF_ENA
CNT_ENA
DMA_ENA
-
Symbol
VALUE
30.4.3 D/A Converter Counter Value register (DACCNTVAL - 0x4008 C008)
30.5.1 DMA counter
30.5.2 Double buffering
Description
16-bit reload value for the DAC interrupt/DMA timer.
This read/write register contains the reload value for the Interrupt/DMA counter.
When the counter enable bit CNT_ENA in DACCTRL is set, a 16-bit counter will begin
counting down, at the rate selected by PCLK_DAC (see
programmed into the DACCNTVAL register. The counter is decremented Each time the
counter reaches zero, the counter will be reloaded by the value of DACCNTVAL and the
DMA request bit INT_DMA_REQ will be set in hardware.
Note that the contents of the DACCTRL and DACCNTVAL registers are read and write
accessible, but the timer itself is not accessible for either read or write.
If the DMA_ENA bit is set in the DACCTRL register, the DAC DMA request will be routed
to the GPDMA. When the DMA_ENA bit is cleared, the default state after a reset, DAC
DMA requests are blocked.
Double-buffering is enabled only if both, the CNT_ENA and the DBLBUF_ENA bits are set
in DACCTRL. In this case, any write to the DACR register will only load the pre-buffer,
which shares its register address with the DACR register. The DACR itself will be loaded
from the pre-buffer whenever the counter reaches zero and the DMA request is set. At the
same time the counter is reloaded with the COUNTVAL register value.
Reading the DACR register will only return the contents of the DACR register itself, not the
contents of the pre-buffer register.
Value Description
1
0
1
0
1
0
1
This bit is cleared on any write to the DACR register.
This bit is set by hardware when the timer times out.
DACR double-buffering is disabled.
When this bit and the CNT_ENA bit are both set, the double-buffering feature in the
DACR register will be enabled. Writes to the DACR register are written to a
pre-buffer and then transferred to the DACR on the next time-out of the counter.
Time-out counter operation is disabled.
Time-out counter operation is enabled.
DMA access is disabled.
DMA Burst Request Input 7 is enabled for the DAC (see
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 30: LPC17xx Digital-to-Analog Converter (DAC)
Table
Table
40), from the value
543).
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0
584 of 840
Reset
Value
0
0
0
0
NA