LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 569

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

28.1 Features
28.2 Applications
UM10360
User manual
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined
amount of time.
For interaction of the on-chip watchdog and other peripherals, especially the reset and
boot-up procedures, please read
•
•
•
•
•
•
•
•
•
UM10360
Chapter 28: LPC17xx Watchdog Timer (WDT)
Rev. 2 — 19 August 2010
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 32-bit timer with internal pre-scaler.
Selectable time period from (T
T
The Watchdog clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the APB peripheral clock (PCLK, see
gives a wide range of potential timing choices for Watchdog operation under different
power reduction conditions. For increased reliability, it also provides the ability to run
the Watchdog timer from an entirely internal source that is not dependent on an
external crystal and its associated components and wiring.
The Watchdog timer can be configured to run in Deep Sleep mode when using the
IRC as the clock source.
WDCLK
× 4.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 3.4 “Reset” on page 18
WDCLK
× 256 × 4) to (T
Table
40), or the RTC oscillator. This
WDCLK
× 2
of this document.
32
× 4) in multiples of
© NXP B.V. 2010. All rights reserved.
User manual
569 of 840