LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 134

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
9.5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4)
Table 116. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094)
[1]
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port 2 pin.
Table 117. GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) bit
[1]
Bit
28
29
30
31
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
31:14 -
Not available on 80-pin package.
Not available on 80-pin package.
Symbol
P0.28EF
P0.29EF
P0.30EF
-
Symbol
P2.0EF
P2.1EF
P2.2EF
P2.3EF
P2.4EF
P2.5EF
P2.6EF
P2.7EF
P2.8EF
P2.9EF
P2.10EF
P2.11EF
P2.12EF
P2.13EF
bit description
description
[1]
[1]
[1]
[1]
All information provided in this document is subject to legal disclaimers.
Value Description
Value Description
0
1
Rev. 2 — 19 August 2010
Enable falling edge interrupt for P0.28.
Enable falling edge interrupt for P0.29.
Enable falling edge interrupt for P0.30.
Reserved.
Enable falling edge interrupt for P2.0
Falling edge interrupt is disabled on P2.0.
Falling edge interrupt is enabled on P2.0.
Enable falling edge interrupt for P2.1.
Enable falling edge interrupt for P2.2.
Enable falling edge interrupt for P2.3.
Enable falling edge interrupt for P2.4.
Enable falling edge interrupt for P2.5.
Enable falling edge interrupt for P2.6.
Enable falling edge interrupt for P2.7.
Enable falling edge interrupt for P2.8.
Enable falling edge interrupt for P2.9.
Enable falling edge interrupt for P2.10.
Enable falling edge interrupt for P2.11.
Enable falling edge interrupt for P2.12.
Enable falling edge interrupt for P2.13.
Reserved.
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
UM10360
© NXP B.V. 2010. All rights reserved.
134 of 840
Reset
value
0
0
0
NA
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NA