EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 10

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Architectural Overview
PS019215-0910
Features
Zilog’s eZ80F91 device is a member of Zilog’s family of eZ80Acclaim!
controllers. The eZ80F91 is a high-speed microcontroller with a maximum clock speed
of 50 MHz and single-cycle instruction fetch. It operates in Z80
ing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the
eZ80F91 makes it suitable for a variety of applications, including industrial control,
embedded communication, and point-of-sale terminals.
Key features of eZ80F91 device include:
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Single-cycle instruction fetch, high-performance, pipelined eZ80
(referred as The CPU in this document)
10/100 BaseT ethernet media access controller with Media-Independent 
Interface (MII)
256 KB Flash memory
16 KB SRAM (8 KB user and 8 KB Ethernet)
Low-power features including SLEEP mode, HALT mode, and selective peripheral
power-down control
Two Universal Asynchronous Receiver/Transmitter (UART) with independent Baud
Rate Generators (BRG)
Serial Peripheral Interface (SPI) with independent clock rate generator
I
IrDA-compliant infrared encoder/decoder
Glueless external peripheral interface with 4 Chip Selects, individual Wait State 
generators, an external WAIT input pin—supports Z80-, Intel-, and Motorola-style
buses
Fixed-priority vectored interrupts (both internal and external) and interrupt controller
Real-time clock with separate V
32 kHz oscillator or external 50/60 Hz input
Four 16-bit Counter/Timers with prescalers and direct input/output drive
Watchdog Timer with internal oscillator clocking option
32 bits of General-Purpose Input/Output (GPIO)
On-Chip Instrumentation (OCI™) and Zilog Debug Interfaces (ZDI)
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C with independent clock rate generator
DD
pin for battery backup and selectable on-chip 
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Product Specification
-compatible address-
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Architectural Overview
CPU core 
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Flash micro-
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