EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 226

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 118. I
PS019215-0910
Code
18h
20h
38h
68h
78h
B0h
Notes
1. W is defined as the Write bit; that is, the lsb is cleared to 0.
2. AAK is an I 2 C control bit that identifies which ACK signal to transmit.
3. R is defined as the Read bit; that is, the lsb is set to 1.
I
Addr+W transmitted
ACK received
Addr+W transmitted,
ACK not received
Arbitration lost
Arbitration lost, 
+W received, 
ACK transmitted
Arbitration lost,
General call address
received, ACK
transmitted
Arbitration lost, 
SLA+R received, 
ACK transmitted
2
C State
2
C Master Transmit Status Codes
If 10-bit addressing is used, the status code is
address, plus the Write bit, are successfully transmitted.
After this interrupt is serviced and the second part of the 10-bit address is transmitted, the
I2C_SR register contains one of the codes listed in
1
3
Microcontroller Response
For a 7-bit address: write byte to DATA,
clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP, clear IFLG
For a 10-bit address: write extended
address byte to data, clear IFLG
Same as code 18h
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
Same as code 68h
Write byte to DATA, clear IFLG, clear AAK
= 0
Or write byte to DATA, clear IFLG, set AAK
= 1
2
18h
or
Table
20h
119.
after the first part of a 10-bit
Next I
Transmit data byte,
receive ACK
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Transmit extended
address byte
Same as code 18h
Return to idle
Transmit START when
bus is free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Same as code 68h
Transmit last byte,
receive ACK
Transmit data byte,
receive ACK
Product Specification
I
2
2
C Serial I/O Interface
C Action
217