EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 58

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

General-Purpose Input/Output
PS019215-0910
GPIO Operation
The eZ80F91 device features 32 General-Purpose Input/Output (GPIO) pins. The GPIO
pins are assembled as four 8-bit ports—Port A, Port B, Port C, and Port D. All port signals
are configured as either inputs or outputs. In addition, all the port pins are used as vectored
interrupt sources for the CPU.
The eZ80F91 microcontroller’s GPIO ports are slightly different from its eZ80
predecessors. Specifically, Port A pins source 8 mA and sink 10 mA. In addition, the 
Port B and C inputs now feature Schmitt-trigger input buffers.
GPIO operation is the same for all four GPIO ports (Ports A, B, C, and D). Each port
features eight GPIO port pins. The operating mode for each pin is controlled by four bits
that are divided between four 8-bit registers. The GPIO mode control registers are:
•
•
•
•
where x can be A, B, C, or D representing any of the four GPIO ports. The mode for each
pin is controlled by setting each register bit pertinent to the pin to be configured. For
example, the operating mode for port B pin 7 (PB7) is set by the values contained in
PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of each
port pin for nine modes. In all modes, reading of the Port x Data register returns the
sampled state or level of the signal on the corresponding pin.
function of each port signal based on these four register bits. After a RESET event, all
GPIO port pins are configured as standard digital inputs with the interrupts disabled.
In addition to the four mode control registers, each port has an 8-bit register, which is used
for clearing edge triggered interrupts. This register is the Port x Alternate register
0(Px_ALT0) where x can be A, B, C, or D representing the four GPIO ports. When a
GPIO pin is configured as an edge triggered interrupt, writing 1 to the corresponding bit of
the Px_ALT0 register clears the interrupt.
Port x Data Register (Px_DR)
Port x Data Direction Register (Px_DDR)
Port x Alternate Register 1 (Px_ALT1)
Port x Alternate Register 2 (Px_ALT2)
Table 6
General-Purpose Input/Output
Product Specification
on page 50 lists the
eZ80F91 MCU
®
49