EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 358

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 240. External I/O Read Timing
PS019215-0910
Parameter
T
T
T
T
T
T
T
1
2
3
4
5
6
7
External I/O Read Timing
ADDR[23:0]
DATA[7:0]
Abbreviation
PHI Clock Rise to ADDR Valid Delay
PHI Clock Rise to ADDR Hold Time
DATA Valid to PHI Clock Rise Setup Time
PHI Clock Rise to DATA Hold Time
PHI Clock Rise to CSx Assertion Delay
PHI Clock Rise to CSx Deassertion Delay
PHI Clock Rise to IORQ Assertion Delay
(input)
IORQ
CSx
Figure 70
signal transition timing is independent of the particular bus mode employed (eZ80
Z80
PHI
RD
®
, Intel, or Motorola).
and
Table 240
T
T
Figure 70. External I/O Read Timing
7
9
T
T
1
5
display the timing for external I/O reads. PHI clock rise/fall to
T
CLK
Minimum
0.0
1.0
0.5
2.0
0.0
2.6
—
T
Delay (ns)
3
T
T
T
2
Maximum
T
6
10
8
7.3
8.5
6.0
7.0
—
—
—
T
4
Product Specification
Electrical Characteristics
®
,
349