EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 293

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 171. Opcode Map—Second Opcode After 0FDh
Legend
PS019215-0910
of Second
First Operand
Opcode
C
D
0
1
2
3
4
5
6
7 LD (IY
8
9
A
B
E
F
Nibble
Upper
Note: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
IYH,B
+d),B
LD
0
Lower Nibble of 2nd Opcode
IY,Mmn
LD IX,
(IY+d)
LD (IY
IYH,C
+d),C
POP
LD
LD
F
IY
1
SP,IY
LD
9
(Mmn),I
LD (IY
IYH,D
+d),D
LD
LD
Y
2
Second Operand
(SP),IY
LD (IY
Mnemonic
IYH,E
+d),E
INC
EX
LD
IY
3
IYH,IYH
LD (IY
(IY+d)
B,IYH
D,IYH
A,IYH
A,IYH
A,IYH
A,IYH
+d),H
ADD
AND
SUB
INC
IYH
INC
OR
LD
LD
LD
4
IYH,IYL
(IY+d)
LD (IY
PUSH
B,IYL
D,IYL
A,IYL
A,IYL
A,IYL
A,IYL
+d),L
DEC
DEC
ADD
AND
SUB
IYH
OR
LD
LD
LD
IY
5
ADD A,
SUB A,
AND A,
LD (IY
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
OR A,
IYH,n
LD B,
LD D,
LD H,
+d),n
LD
6
Lower Nibble (Hex)
LD BC,
LD DE,
LD HL,
LD (IY
(IY+d)
(IY+d)
(IY+d)
LD IY,
(IY+d)
IYH,A
+d),A
LD
7
IYL,B
LD
8
IY,BC
IY,DE
IY,SP
IYL,C
SP,IY
ADD
ADD
ADD
ADD
IY,IY
(IY)
LD
LD
JP
9
(Mmn)
IYL,D
LD
LD
IY,
A
Table
IYL,E
173
DEC
LD
IY
B
Product Specification
IYL,IYH
eZ80
C,IYH
E,IYH
A,IYH
A,IYH
A,IYH
A,IYH
A,IYH
ADC
SBC
XOR
INC
IYL
LD
LD
LD
LD
CP
C
®
IYL,IYL
CPU Instruction Set
C,IYL
E,IYL
A,IYL
A,IYL
A,IYL
A,IYL
A,IYL
DEC
ADC
XOR
SBC
IYL
CP
LD
LD
LD
LD
D
ADC A,
XOR A,
SBC A,
LD (IY
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
+d),IX
LD C,
CP A,
LD E,
LD A,
IYL,n
LD L,
LD
E
+d),BC
+d),DE
+d),HL
LD (IY
LD (IY
LD (IY
LD (IY
+d),IY
IYL,A
LD
F
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