EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 236

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 128. I
PS019215-0910
Bit 
Position
5
STA
4
STP
3
IFLG
2
AAK
[1:0]
Bit
Reset
CPU Access
Note: R = Read only.
Bit 
Position
[7:3]
STAT
[2:0]
2
C Status Registers
I
The I
MSbs; the three LSbs are always 0. The Read Only I2C_SR registers share the same I/
O addresses as the Write Only I2C_CCR registers. See
There are 29 possible status codes, as listed in
contains the status code
generated, and the IFLG bit in the I
correspond to a defined state of the I
2
C Status Register
Value Description
0
1
0
1
0
1
0
1
00
Value
00000–
11111
000
2
C_SR register is a Read Only register that contains a 5-bit status code in the five
Master mode START condition is sent.
Master mode start-transmit START condition on the bus.
Master mode STOP condition is sent.
Master mode stop-transmit STOP condition on the bus.
I
I
Not Acknowledge.
Acknowledge.
Reserved.
R
7
1
2
2
C interrupt flag is not set.
C interrupt flag is set.
Description
5-bit I
Reserved.
R
6
1
2
(I2C_SR = 00CCh)
C status code.
F8h
R
5
1
, no relevant status information is available, no interrupt is
2
R
4
1
C_CTL register is not set. All other status codes
2
C.
R
3
1
Table
R
2
0
129. When the I
Table
R
1
0
128.
Product Specification
R
0
0
2
I
C_SR register
2
C Serial I/O Interface
227