EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 312

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 185. EMAC Configuration Register 4
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit 
Position
7
6
TPCF
5
THDF
4
PARF
3
RxFC
2
TxFC
1
TPAUSE
0
RxEN
EMAC Configuration Register 4
The EMAC Configuration Register 4 controls pause control frame behavior, back
pressure, and receive frame acceptance. See
Value
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Reserved.
Do not transmit a pause control frame.
Transmit pause control frame (FULL-DUPLEX mode). TPCF
continually sends pause control frames until negated.
Disable back pressure.
EMAC asserts back pressure on the link. Back pressure
causes preamble to be transmitted, raising carrier sense
(HALF-DUPLEX mode).
Only accept frames that meet preset criteria (that is, address,
CRC, length, etc.).
All frames are received regardless of address, CRC, length,
etc.
EMAC ignores received pause control frames.
EMAC acts upon pause control frames received.
PAUSE control frames are not allowed to be transmitted.
PAUSE control frames are allowed to be transmitted.
Do not force a pause condition.
Force a pause condition while this bit is asserted.
EMAC receiver disabled.
EMAC receiver enabled.
R
7
0
R/W
6
0
R/W
5
0
(EMAC_CFG4 = 0024h)
R/W
4
0
R/W
3
0
Table
185.
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
303