EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 95

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 28. Chip Select x Upper Bound Register (CS0_UBR = 00A9h, CS1_UBR = 00ACh,
CS2_UBR = 00AFh, CS3_UBR = 00B2h)
PS019215-0910
Bit
CS0_UBR Reset
CS1_UBR Reset
CS2_UBR Reset
CS3_UBR Reset
CPU Access
Note: R/W = Read/Write.
Bit 
Position
[7:0]
CSX_UBR
Chip Select x Upper Bound Register
For Memory chip selects, the Chip Select x Upper Bound registers, listed in
defines the upper bound of the address range for which the corresponding Chip Select (if
enabled) are active. For I/O chip selects, this register produces no effect. The reset state for
the Chip Select 0 Upper Bound register is
Select Upper Bound registers is
Value Description
00h–
FFh
R/W
For Memory Chip Selects (CSx_IO = 0)
This byte specifies the upper bound of the chip select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a chip select signal must be generated.
For I/O Chip Selects (CSx_IO = 1)
No effect.
7
1
0
0
0
R/W
6
1
0
0
0
R/W
5
1
0
0
0
00h
R/W
4
1
0
0
0
.
FFh
R/W
3
1
0
0
0
when the reset state for the other Chip
R/W
2
1
0
0
0
R/W
1
1
0
0
0
Chip Selects and Wait States
Product Specification
R/W
0
1
0
0
0
eZ80F91 MCU
Table
28,
86