EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 139

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Timer Registers
The CPU monitors and controls the timer using seven 8-bit registers. These registers are
the control register, the interrupt identification register, the interrupt enable register and
the reload register pair (High and Low byte). There are also a pair of data registers used to
read the current timer count value.
The variable x can be 0, 1, 2, or 3 to represent each of the four available timers.
Basic Timer Register Set
Each timer requires a different set of registers for configuration and control. However,
all timers contain the following seven registers, each of which is necessary for basic 
operation:
•
•
•
•
•
The Timer Data Register is Read Only, when the Timer Reload Register is Write Only.
The address space for these two registers is shared.
Register Set for Capture in Timer 1
In addition to the basic register set, Timer 1 uses the following five registers for its INPUT
CAPTURE mode:
•
•
Register Set for Capture/Compare/PWM in Timer 3
In addition to the basic register set, Timer 3 uses 19 registers for INPUT CAPTURE,
OUTPUT COMPARE, and PWM modes. PWM and capture/compare functions cannot be
used simultaneously so, their register address space is shared. INPUT CAPTURE and
OUTPUT COMPARE are used concurrently and their address space is not shared.
The INPUT CAPTURE mode registers are equivalent to those used in Timer 1 above
(substitute TMR3 for TMR1).
OUTPUT COMPARE mode uses the following nine registers:
•
Timer Control Register (TMRx_CTL)
Interrupt Identification Register (TMRx_IIR)
Interrupt Enable Register (TMRx_IER)
Timer Data Registers (TMRx_DR_H and TMRx_DR_L)
Timer Reload Registers (TMRx_RR_H and TMRx_RR_L)
Capture Control Register (TMR1_CAP_CTL)
Capture Value Registers (TMR1_CAP_B_H, TMR1_CAP_B_L, TMR1_CAP_A_H,
TMR1_CAP_A_L)
Output Compare Control Registers
–
TMR3_OC_CTL1
Programmable Reload Timers
Product Specification
eZ80F91 MCU
130