EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 33

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
137
138
139
140
141
142
BGA
Pin No Symbol
A4
E6
B4
D5
C4
A3
Rx_DV
RxD0
RxD1
RxD2
RxD3
MDC
Function
MII Receive
Data Valid
MII Receive
Data
MII Receive
Data
MII Receive
Data
MII Receive
Data
MII
Management
Data Clock
Signal Direction Description
Input
Input
Input
Input
Input
Output
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data Valid is provided by the
MII PHY interface synchronous to the
rising-edge of Rx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
This pin is used by the Ethernet MAC
for the MII Management Interface to
the PHY. The Ethernet MAC provides
the MII Management Data Clock to
the MII PHY interface.
Product Specification
Architectural Overview
24