EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 156

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
T3 Count
PWM0
PWM0
PWM1
PWM1
System Clock
Clock Enable
T3 Count
0
The inverted PWM outputs PWM0, PWM1, PWM2, and PWM3 are globally enabled by
setting TMR3_PWM_CTL1[PAIR_EN] to 1. The individual PWM generators must be
enabled for the associated inverted PWM signals to be output.
For each of the 4 PWM generators, there is a 16-bit rising edge value
{TMR3_PWMxR_H[PWMxR_H], TMR3_PWMxR_L[PWMxR_L]} and a 16-bit falling
edge value {TMR3_PWMxF_H[PWMxF_H], TMR3_PWMxF_L[PWMxF_L]} for a total
of 16 registers. The rising-edge byte pairs define the timer count at which the PWMx 
output transitions from Low to High. Conversely, the falling-edge byte pairs define the
timer count at which the PWMx output transitions from High to Low. On reset, all enabled
PWM outputs begin Low and all PWMx outputs begin High. When the PWMx output is
Low, the logic is looking for a match between the timer count and the rising edge value,
and vice versa. Therefore, in a case in which the rising edge value is the same as the falling
edge value, the PWM output frequency is one-half the rate at which the counter passes
through its entire count cycle (from reload value down to
Figure
timing, respectively. Associated control values are listed in
Figure 32. Multi-PWM Operation—Expanded View of Timing
C B A 9 8 7 6 5 4 3 2 1 C B A 9 8 7 6 5 4 3 2 1 C B A
31and
Figure 32
A
Figure 31. Multi-PWM Operation
display a simple Multi-PWM output and an expanded view of the
9
8
7
0000h
Table 71
6
9 8 7 6 5 4 3 2 1
Programmable Reload Timers
Product Specification
).
on page 148.
5
eZ80F91 MCU
C B A
4
147