EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 32

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
127
128
129
130
131
132
133
134
135
136
BGA
Pin No Symbol
C7
D7
A6
B6
C6
E7
A5
B5
D6
C5
TxD2
TxD1
TxD0
Tx_EN
Tx_CLK
Tx_ER
V
V
Rx_ER
Rx_CLK
DD
SS
Function
MII Transmit
Data
MII Transmit
Data
MII Transmit
Data
MII Transmit
Enable
MII Transmit
Clock
MII Transmit
Error
Power Supply
Ground
MII Receive
Error
MII Receive
Clock
Signal Direction Description
Output
Output
Output
Output
Input
Output
Input
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Enable is synchronous to the
rising-edge of Tx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Clock is the Nibble or
Symbol Clock provided by the MII
PHY interface.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Error is synchronous to the
rising-edge of Tx_CLK.
Power Supply.
Ground.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Error is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Clock is the Nibble or Symbol
Clock provided by the MII PHY
interface.
Product Specification
Architectural Overview
23