EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 13

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 1. eZ80F91 144-BGA Pin Configuration
PS019215-0910
M PD0
Note: Lowercase n suffix indicates an active-low signal in this table only
A SDA SCL
B
C PB6
D PB1
G V
H X
K PD5
E PC7
F PC3
L PD1
J
V
V
12
OUT
SS
SS
SS
Pin Description
PC4
PC0
PD6
PD2 TRSTn TCK
PB7
PB3
V
V
V
PHI
X
11
DD
DD
SS
IN
Table 1
LOOP
FILT_
PLL_
OUT
TDO
PC5
PC1
PD3
PA0
PA1
V
PB5
PB0
V
10
DD
DD
lists the pin configuration of the eZ80F91 device in the 144-BGA package.
HALT
SLPn
PB4
PC2
PD4 TRIGOUT
PA4
PA3
PA5
V
V
V
TDI
9
DD
_
SS
SS
XOUT
RTC_
RTC_
CRS
PC6
PD7
PA7
V
PA2
PB2
V
V
XIN
8
DD
SS
SS
BUSREQn INSTRDn IORQn
BUSACKn
Tx_ER
RTC_
TxD3
TxD2
TxD1
PLL_
COL
TMS
PA6
V
V
V
7
DD
DD
SS
RESETn
Tx_CLK
Rx_ER
Tx_EN
WAITn
RxD0
TxD0
NMIn
V
V
A9
6
SS
SS
MREQn
RxD2
WRn
CLK
RDn
V
V
Rx_
A17
A23
D5
A5
5
DD
SS
Rx_DV MDC
RxD1 MDIO
RxD3
A15
A20
V
A11
V
A4
D2
D6
D7
4
DD
SS
Product Specification
CS0n
V
A14
V
A21
D1
D4
D3
A3
A8
Architectural Overview
3
SS
SS
CS2n CS1n
WPn
V
A13
V
A19
V
V
V
A2
A6
D0
2
SS
DD
DD
DD
SS
CS3n
V
A10
A12
A16
A18
A22
V
A0
A1
A7
1
DD
DD
4