EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 273

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 151. Pin to Boundary Scan Cell Mapping (Continued)
PS019215-0910
Pin
MII_Tx_ER
MII_Tx_CLK
MII_Tx_EN
MII_TxD0
MII_TxD1
Notes
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
2. Direction on the data bus is controlled by a single output enable. It is associated in this table with D[0].
3. MREQ,
associated with the LSb that they control.
IORQ
Usage
Boundary scan functionality is utilized by issuing the appropriate Test Access Port (TAP)
instruction and shifting data accordingly. Both of these steps are accomplished using the
JTAG interface. To activate the TAP (see
be driven Low at least two CPU system clock cycles prior to the deassertion of the RESET
pin. Otherwise the OCI-JTAG features are disabled.
As per the IEEE 1149.1 specification, the boundary scan cells capture system I/O on the
rising edge of TCK during the CAPTURE_DR state. This captured data is shifted on the
rising edge of TCK while in the SHIFT_DR state. Pins and logic receive shifted data only
when enabled, and only on the falling edge of TCK during the UPDATE_DR state, after
shifting is completed.
For more information about eZ80F91 boundary scan support, refer to Using BSDL Files
with eZ80
Boundary Scan Instructions
The eZ80F91 device’s boundary scan architecture supports the following instructions:
•
•
•
•
•
, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
BYPASS (required)
SAMPLE (required)
EXTEST (required)
PRELOAD (required)
IDCODE (optional)
Direction
Output
Output
Output
Output
Input
®
and eZ80Acclaim!
Scan Cell No
102
103
104
105
106
®
Devices (AN0114).
Pin
PD1
PD0
PD0
PD0
OCI Activation
on page 258), the TCK pin must
Direction
Output
Product Specification
Input
OEN
OEN
On-Chip Instrumentation
eZ80F91 MCU
Scan Cell No
209
210
212
211
264