EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 199

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 105. UART Modem Control Registers
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit 
Position
7
6
POLARITY
5
MDM
4
LOOP
Table 104. Parity Select Definition for Multidrop Communications
UART Modem Control Register
This register is used to control and check the modem status. See
Note: *In Multidrop Mode, EPS resets to 0 after the first character is sent.
Value
0
0
1
0
1
0
1
Multidrop Mode
Description
Reserved.
TxD and RxD signals—Normal Polarity.
Invert Polarity of TxD and RxD signals.
Multidrop Mode disabled.
Multidrop Mode enabled. See
definitions.
LOOP BACK mode is not enabled.
LOOP BACK mode is enabled.
The UART operates in internal LOOP BACK mode. The transmit data output
port is disconnected from the internal transmit data output and set to 1. The
receive data input port is disconnected and internal receive data is connected to
internal transmit data. The modem status input ports are disconnected and the
four bits of the modem control register are connected as modem status inputs.
The two modem control output ports (OUT1&2) are set to their inactive state.
0
0
1
1
R
7
0
R/W
6
0
Even Parity Select
R/W
5
0
1*
R/W
0
1
0
(UART0_MCTL = 00C4h, UART1_MCTL = 00D4h)
4
0
Table 104
R/W
3
0
Universal Asynchronous Receiver/Transmitter
on page 189 for parity select
R/W
2
0
Parity Type
space
mark
even
odd
R/W
1
0
Product Specification
Table
R/W
0
0
105.
eZ80F91 MCU
190