EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 235

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 127. I
PS019215-0910
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit 
Position
7
IEN
6
ENAB
2
C Control Register
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I
ates as if a STOP condition is received, but no STOP condition is transmitted. If both STA
and STP bits are set, the I
mode), then transmits the START condition. The STP bit is cleared to 0 automatically.
Writing a 0 to this bit produces no effect.
The I
I
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I
the Low period of the I
When a 0 is written to IFLG, the interrupt is cleared and the I
When the I
acknowledge clock pulse on the I
•
•
•
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If AAK is cleared to 0 in SLAVE TRANSMIT mode, the byte in the
I
block enters the
to its slave address unless AAK is set to 1. See
2
2
C states is entered. The only state that does not set the IFLG bit is state
C_DR register is assumed to be the final byte. After this byte is transmitted, the I
Value Description
0
1
0
1
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad-
dress is received.
The general call address is received and the General Call Enable bit in I
to 1.
A data byte is received while in MASTER or SLAVE modes.
2
C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
R/W
2
I
I
The I
The I
7
0
C Acknowledge bit (AAK) is set to 1, an acknowledge is sent during the
2
2
C interrupt is disabled.
C interrupt is enabled.
C8h
2
2
C bus (SCL/SDA) is disabled and all inputs are ignored.
C bus (SCL/SDA) is enabled.
R/W
2
6
0
C bus. If the STP bit is set to 1 in SLAVE mode, the I
(I2C_CTL = 00CBh)
state, then returns to an idle state. The I
2
C bus clock line is stretched and the data transfer is suspended.
2
R/W
C block first transmits the STOP condition (if in MASTER
5
0
2
C bus if:
R/W
4
0
R/W
3
0
Table 127
R/W
2
0
on page 226.
2
R
1
0
2
C module does not respond
C clock line is released.
Product Specification
R
0
0
I
2
C Serial I/O Interface
2
F8h
C module oper-
2
C_SAR is set
. If IFLG is
2
C
2
C,
226