EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 16

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
BGA
Pin No Symbol
F1
F2
F3
F4
G1
G2
G3
F5
H1
H2
G4
H3
J1
G5
J2
H4
J3
K1
K2
L1
M1
M2
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
V
V
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
V
V
CS0
CS1
CS2
CS3
V
V
DD
SS
DD
SS
DD
SS
Function
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Chip Select 0
Chip Select 1
Chip Select 2
Chip Select 3
Power Supply
Ground
Signal Direction Description
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output, Active
Low
Output, Active
Low
Output, Active
Low
Output, Active
Low
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
Power Supply.
Ground.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
Power Supply.
Ground.
CS0 Low indicates that an access is
occurring in the defined CS0 memory
or I/O address space.
CS1 Low indicates that an access is
occurring in the defined CS1 memory
or I/O address space.
CS2 Low indicates that an access is
occurring in the defined CS2 memory
or I/O address space.
CS3 Low indicates that an access is
occurring in the defined CS3 memory
or I/O address space.
Power Supply.
Ground.
Product Specification
Architectural Overview
7