EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 237

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 129. I
PS019215-0910
Code
00h
08h
10h
18h
20h
28h
30h
38h
40h
48h
50h
58h
60h
68h
70h
78h
80h
88h
90h
98h
A0h
A8h
B0h
B8h
C0h
C8h
D0h
Status
Bus error.
START condition transmitted.
Repeated START condition transmitted.
Address and Write bit transmitted, ACK received.
Address and Write bit transmitted, ACK not received.
Data byte transmitted in MASTER mode, ACK received.
Data byte transmitted in MASTER mode, ACK not received.
Arbitration lost in address or data byte.
Address and Read bit transmitted, ACK received.
Address and Read bit transmitted, ACK not received.
Data byte received in MASTER mode, ACK transmitted.
Data byte received in MASTER mode, NACK transmitted.
Slave address and Write bit received, ACK transmitted.
Arbitration lost in address as master, slave address and Write bit received, ACK transmitted.
General Call address received, ACK transmitted.
Arbitration lost in address as master, General Call address received, ACK transmitted.
Data byte received after slave address received, ACK transmitted.
Data byte received after slave address received, NACK transmitted.
Data byte received after General Call received, ACK transmitted.
Data byte received after General Call received, NACK transmitted.
STOP or repeated START condition received in SLAVE mode.
Slave address and Read bit received, ACK transmitted.
Arbitration lost in address as master, slave address and Read bit received, ACK transmitted.
Data byte transmitted in SLAVE mode, ACK received.
Data byte transmitted in SLAVE mode, ACK not received.
Last byte transmitted in SLAVE mode, ACK received.
Second Address byte and Write bit transmitted, ACK received.
2
C Status Codes
When each of these states is entered, the corresponding status code appears in this register
and the IFLG bit in the I
tus code returns to
F8h
.
2
C_CTL register is set to 1. When the IFLG bit is cleared, the sta-
Product Specification
I
2
C Serial I/O Interface
228