EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 211

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
SPI Signals
The four basic SPI signals are:
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These SPI signals are discussed in the following paragraphs. Each signal is described in
both MASTER and SLAVE modes.
Master In, Slave Out
The Master In, Slave Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the most-
significant bit (msb) sent first. The MISO pin of a slave device is placed in a high-imped-
ance state if the slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master Out, Slave In
The Master Out, Slave In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the msb
sent first. When the SPI is not enabled, this signal is in a high-impedance state.
Slave Select
The active Low Slave Select (SS) input signal is used to select the SPI as a slave device. It
must be Low prior to all data communication and must stay Low for the duration of the
data transfer.
The SS input signal must be High for the SPI to operate as a master device. If the SS signal
goes Low in Master mode, a Mode Fault error flag (MODF) is set in the SPI_SR register.
For more information, see
When the clock phase (CPHA) is set to 0, the shift clock is the logical OR of SS with
SCK. In this clock phase mode, SS must go High between successive characters in an
SPI message. When CPHA is set to 1, SS remains Low for several SPI characters. In
cases where there is only one SPI slave, its SS line could be tied Low as long as CPHA
is set to 1. For more information on CPHA, see
Serial Clock
The Serial Clock (SCK) is used to synchronize data movement both in and out of the
device via its MOSI and MISO pins. The master and slave are each capable of exchanging
a byte of data during a sequence of eight clock cycles. Because SCK is generated by the
master, the SCK pin becomes an input on a slave device. The SPI contains an internal
MISO (Master In, Slave Out)
MOSI (Master Out, Slave In)
SCK (SPI Serial Clock)
SS (Slave Select)
SPI Status Register
on page 209.
SPI Control Register
Product Specification
Serial Peripheral Interface
on page 208.
eZ80F91 MCU
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