EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 80

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 19. Z80 Bus Mode Read States
Table 20. Z80 Bus Mode Write States
PS019215-0910
STATE T1
STATE T2
STATE T3
STATE T1
STATE T2
STATE T3
eZ80
Z80
®
The Write cycle begins in State T1. The
The Read cycle begins in State T1. The
the associated chip select signal is asserted.
During State T2, the RD signal is asserted. Depending on the instruction, either the MREQ
or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU system
clock cycle prior to the end of State T2, additional Wait states (T
WAIT pin is driven High.
During State T3, no bus signals are altered. The data is latched by the eZ80F91 at the rising
edge of the CPU system clock at the end of State T3.
the associated chip select signal is asserted.
During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional wait states (T
until the WAIT pin is driven High.
During State T3, no bus signals are altered.
®
Bus Mode
CPU system clock cycles per bus mode state is also independently programmable. For
Intel bus mode, multiplexed address and data are selected in which both the lower byte of
the address and the data byte use the data bus, DATA[7:0]. Each of the bus modes are
explained in the following sections.
Chip selects configured for eZ80 bus mode do not modify the bus signals from the CPU.
The timing diagrams for external Memory and I/O Read and Write operations are shown in
the
Chip selects configured for Z80 mode modify the eZ80 bus signals to match the Z80 micro-
processor address and data bus interface signal format and timing. During Read operations,
the Z80 Bus mode employs three states—T1, T2, and T3 as listed in
During Write operations, Z80 Bus mode employs three states—T1, T2, and T3 as listed in
Table
Bus Mode
AC Characteristics
20.
on page 344. The default mode for each chip select is eZ80 mode.
CPU
CPU
drives the address onto the address bus, and
drives the address onto the address bus and
WAIT
Chip Selects and Wait States
Product Specification
) are asserted until the
Table
WAIT
) are asserted
eZ80F91 MCU
19.
71