EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 84

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 21. Intel Bus Mode Read States—Separate Address and Data Buses (Continued)
Table 22. Intel Bus Mode Write States—Separate Address and Data Buses
PS019215-0910
STATE T3
STATE T4
STATE T1
STATE T2
STATE T3
STATE T4
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
The CPU deasserts the WR signal at the beginning of State T4. The CPU holds the data
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD
signal and completes the Intel bus mode cycle.
The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated chip select signal is asserted, and the data is driven onto the data bus. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
During State T2, the CPU asserts the WR signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
and address buses till the end of T4. The bus cycle is completed at the end of T4.
WAIT
WAIT
During Write operations with separate address and data buses, the Intel bus mode employs
four states—T1, T2, T3, and T4 as listed in
Intel bus mode timing is displayed for a Read operation in
Write operation in
driven Low prior to the beginning of State T3, additional wait states (T
until the READY signal is driven High. The Intel bus mode states are configured for 2 to
15 CPU system clock cycles. In the
Intel bus mode state is 2 CPU system clock cycles in duration.
Figure 14
peripheral.
) are asserted until the READY pin is driven High.
) are asserted until the READY pin is driven High.
on page 77 also display the assertion of one Wait state (T
Figure 14
on page 77. If the READY signal (external WAIT pin) is
Figure 13
Table
on page 76 and
22.
Figure 13
Figure 14
Figure 13
Chip Selects and Wait States
Product Specification
WAIT
on page 76 and for a
WAIT
on page 77, each
) by the selected
on page 76 and
eZ80F91 MCU
) are asserted
75