EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 26

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
100
101
102
BGA
Pin No Symbol
E10
D12
F8
PB0
IC0
EC0
PB1
IC1
PB2
SS
Function
GPIO Port B
Input Capture
Event Counter Schmitt-trigger
GPIO Port B
Input Capture
GPIO Port B
SPI Slave
Select
Signal Direction Description
Bidirectional with
Schmitt-trigger
input
Schmitt-trigger
input
input
Bidirectional with
Schmitt-trigger
input
Schmitt-trigger
input
Bidirectional with
Schmitt-trigger
input
Schmitt-trigger
input, Active Low
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
Input Capture A Signal to Timer 1.
This signal is multiplexed with PB0.
Event Counter Signal to Timer 1. This
signal is multiplexed with PB0.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
Input Capture B Signal to Timer 1.
This signal is multiplexed with PB1.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
The slave select input line is used to
select a slave device in SPI mode.
This signal is multiplexed with PB2.
Product Specification
Architectural Overview
17