EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 227

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 119. I
PS019215-0910
Code
38h
68h
B0h
D0h
D8h
Notes
1. W is defined as the Write bit; that is, the lsb is cleared to 0.
2. AAK is an I 2 C control bit that identifies which ACK signal to transmit.
3. R is defined as the Read bit; that is, the lsb is set to 1.
I
Arbitration lost
Arbitration lost,
SLA+W received,
ACK transmitted
Arbitration lost,
SLA+R received,
ACK transmitted
Second address byte
+ W transmitted,
ACK received
Second address byte
+ W transmitted,
ACK not received
2
C State
2
C 10-Bit Master Transmit Status Codes
If a repeated START condition is transmitted, the status code is
each data byte is transmitted, the IFLG is set to 1 and one of the status codes listed in
Table 120
is loaded into the I2C_SR register.
1
3
Microcontroller Response
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, clear AAK = 0
Or clear IFLG, set AAK = 1
Write byte to DATA,
clear IFLG, clear AAK = 0
Or write byte to DATA,
clear IFLG, set AAK = 1
Write byte to data,
clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
Same as code D0h
2
Next I
Return to idle
Receive data byte, transmit NACK
Transmit last byte,
receive ACK
Transmit data byte,
receive ACK
Transmit data byte,
receive ACK
Transmit STOP
Transmit STOP then
START
Same as code D0h
Transmit START when bus free
Receive data byte, transmit ACK
Transmit repeated START
2
C Action
10h
Product Specification
instead of
I
2
C Serial I/O Interface
08h
. After
218