EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 233

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 124. I
Table 125. I
PS019215-0910
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit 
Position
[7:1]
SLA
0
GCE
Bit
Reset
CPU Access
Note: R/W = Read/Write.
2
2
C Slave Address Register
C Extended Slave Address Register
point). After the next byte of the address (I
interrupt and enters SLAVE mode.Then I
10-bit extended address. The full 10-bit address is supplied by {I
I
I
The I
bit addressing of the I
bits of the 10-bit slave address. The full 10-bit address is supplied by {I
I
When the register receives an address starting with
the I
ACK after receiving the I
point). After the next byte of the address (I
interrupt and enters SLAVE mode.Then I
10-bit extended address. The full 10-bit address is supplied by {I
I
2
2
2
2
C Extended Slave Address Register
C_XSAR[7:0]}. See
C_XSAR[7:0]}.
C_XSAR[7:0]}. See
Value
00h–7Fh 7-bit slave address or upper 2 bits, I
0
1
2
2
C recognizes that a 10-bit slave addressing mode is being selected. The I
C_XSAR register is used in conjunction with the I
R/W
R/W
7
0
7
0
Description
address when operating in 10-bit mode.
I
I
2
2
C not enabled to recognize the General Call Address.
C enabled to recognize the General Call Address.
R/W
R/W
6
0
6
0
2
C when in SLAVE mode. The I
Table
Table
2
R/W
C_XSAR byte (the device does not generate an interrupt at this
R/W
5
0
5
0
124.
(I2C_SAR = 00C8h)
125.
R/W
R/W
4
0
4
0
(I2C_XSAR = 00C9h)
2
2
C_SAR[2:1] are used as the upper 2 bits for the
C_SAR[2:1] are used as the upper 2 bits for the
2
R/W
2
R/W
C_XSAR) is received, the I
C_XSAR) is received, the I
3
0
3
0
2
R/W
R/W
C_SAR[2:1], of
F7h
2
0
2
0
2
C_SAR value forms the lower 8
to
2
C_SAR register to provide 10-
F0h
R/W
R/W
1
0
1
0
(I
Product Specification
2
2
2
C_SAR[7:3] = 11110b),
C_SAR[2:1],
C_SAR[2:1],
R/W
R/W
0
0
0
0
I
2
C Serial I/O Interface
2
2
2
C generates an
C generates an
C_SAR[2:1],
2
C sends an
224