EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 308

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 181. EMAC Configuration Register 1
PS019215-0910
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit 
Position
7
PADEN
6
ADPADN
5
VLPAD
4
CRCEN
3
FULLD
2
FLCHK
1
HUGEN
EMAC Configuration Register 1
The EMAC Configuration Register 1 allows control of the padding, autodetection, cyclic
redundancy checking (CRC) control, full-duplex, field length checking, maximum packet
ignores, and proprietary header options. See
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
No padding. Assume all frames presented to EMAC have
proper length.
EMAC pads all short frames by adding zeroes to the end of the
data field. This bit is used in conjunction with ADPADN and
VLPAD.
Disable autodetection.
Enable frame detection by comparing the two bytes following
the source address with 0x8100 (VLAN Protocol ID) and pad
accordingly. This bit is ignored if PADEN is cleared to 0.
Do not pad all short frames.
EMAC pads all short frames to 64 bytes and append a valid
CRC. This bit is ignored if PADEN is cleared to 0.
Do not append CRC.
Append CRC to every frame regardless of padding options.
HALF-DUPLEX mode. CSMA/CD is enabled.
Enable FULL-DUPLEX mode. CSMA/CD is disabled.
Ignore the length field within Transmit/Receive frames.
Both Transmit and Receive frame lengths are compared to the
length/type field. If the length/type field represents a length
then the frame length check is performed.
Limit the Receive frame-size to the number of bytes specified
in the MAXF[15:0] field.
Allow unlimited sized frames to be received. Ignore the
MAXF[15:0] field.
R/W
7
0
R/W
6
0
R/W
5
0
(EMAC_CFG1 = 0021h)
R/W
4
0
R/W
3
0
Table
181.
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
299