EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 310

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 183. EMAC Configuration Register 2
PS019215-0910
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit 
Position
7
BPNB
6
NOBO
[5:0]
LCOL
EMAC Configuration Register 2
The EMAC Configuration Register 2 controls the behavior of the back pressure and late
collision data from the Descriptor table. See
Value
0
1
0
1
00h–3Fh Sets the number of bytes after Start Frame Delimiter (SFD) for
R/W
Description
Use normal back-off algorithm prior to transmitting packet. No
back pressure applied.
After incidentally causing a collision during back pressure, the
EMAC immediately (that is, no back-off) retransmits the packet
without back-off, which reduces the chance of further collisions
and ensures that the Transmit packets are sent.
Enable exponential back-off.
The EMAC immediately retransmits following a collision rather
than use the binary exponential backfill algorithm, as specified
in the IEEE 802.3 specification.
which a late collision occurs. By default, all late collisions are
aborted.
7
0
R/W
6
0
R/W
5
1
(EMAC_CFG2 = 0022h)
R/W
4
1
R/W
3
0
Table
183.
R/W
2
1
R/W
Ethernet Media Access Controller
1
1
Product Specification
R/W
0
1
301