EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 145

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Timer Data Register—Low Byte
The Timer x Data Register—Low Byte returns the Low byte of the current count value of
the selected timer. The Timer Data Register—Low Byte (see
timer is in operation. Reading the current count value does not affect timer 
operation. To read the 16-bit data of the current count value, {TMRx_DR_H[7:0],
TMRx_DR_L[7:0]}, first read the Timer Data Register—Low Byte, followed by the
Timer Data Register—High Byte. The Timer Data Register—High Byte value is latched
into temporary storage when a Read of the Timer Data Register—Low Byte occurs.
This register shares its address with the corresponding timer reload register.
Table 57. Timer Data Register—Low Byte
0068h, TMR2_DR_L = 0072h, TMR3_DR_L = 0077h)
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMR_DR_L
Value
00h–FFh
R
7
0
Description
These bits represent the Low byte of the 2-byte timer data
value, {TMR
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.
R
6
0
x
_DR_H[7:0], TMR
R
5
0
(TMR0_DR_L = 0063h, TMR1_DR_L =
R
4
0
R
3
0
Table
x
Programmable Reload Timers
_DR_L[7:0]}. Bit 7 is bit 7
Product Specification
57) is read when the
R
2
0
eZ80F91 MCU
R
1
0
R
0
0
136