EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 31

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
120
121
122
123
124
125
126
BGA
Pin No Symbol
F7
A8
B8
C8
D8
A7
B7
PA6
PWM2
EC1
PA7
PWM3
V
V
CRS
COL
TxD3
DD
SS
Function
GPIO Port A
PWM Output 2
Inverted
Event Counter Input
GPIO Port A
PWM Output 3
Inverted
Power Supply
Ground
MII Carrier
Sense
MII Collision
Detect
MII Transmit
Data
Signal Direction Description
Bidirectional
Output
Bidirectional
Output
Input
Input
Output
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
This pin is used by Timer 3 for
negative PWM 2. This signal is
multiplexed with PA6.
Event Counter Signal to Timer 2. This
signal is multiplexed with PA6.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
This pin is used by Timer 3 for
negative PWM 3. This signal is
multiplexed with PA7.
Power Supply.
Ground.
This pin is used by the EMAC for the
MII Interface to the PHY (physical
layer). Carrier Sense is an
asynchronous signal.
This pin is used by the EMAC for the
MII Interface to the PHY. Collision
Detect is an asynchronous signal.
This pin is used by the EMAC for the
MII Interface to the PHY. Transmit
Data is synchronous to the rising-
edge of Tx_CLK.
Product Specification
Architectural Overview
22