EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 335

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 217. EMAC PHY Read Status Data Register—Low Byte
PS019215-0910
Bit
Position
1
Tx_CF_STAT
0
Tx_DONE_STAT
Bit
Reset
CPU Access
Note: R = Read Only.
Bit 
Position
[7:0]
EMAC_PRSD_L
EMAC PHY Read Status Data Register—Low and High Bytes
The PHY MII Management Data Register is where the data Read from the PHY is stored.
See
Value
00h–FFh These bits represent the Low byte of the 2 byte EMAC PHY
Table 217
Value
1
0
1
0
R
7
0
Description
Read Status Data value, {EMAC_PRSD_H,
EMAC_PRSD_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit
0 (lsb) of the 16 bit value.
and
Description
Transmit Control Frame Interrupt (Transmit Interrupt)
occurs.
Transmit Control Frame Interrupt (Transmit Interrupt)
does not occur.
Transmit Done interrupt (Transmit Interrupt) occurs.
Transmit Done interrupt (Transmit Interrupt) does not
occur.
Table 218
R
6
0
R
5
0
on page 327.
R
4
0
R
3
0
R
2
0
(EMAC_PRSD_L = 004Eh)
Ethernet Media Access Controller
R
1
0
Product Specification
R
0
0
326