EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 22

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
78
79
80
81
82
83
84
85
BGA
Pin No Symbol
K12
K11
H8
J11
J12
J10
G7
H12
PD5
DSR0
PD6
DCD0
PD7
RI0
V
V
LOOP_FILT PLL Loop Filter Analog
PLL_V
X
DD
SS
OUT
SS
Function
GPIO Port D
Data Set
Ready
GPIO Port D
Data Carrier
Detect
GPIO Port D
Ring Indicator Input, Active Low Modem status signal to the UART.
Power Supply
Ground
Ground
System Clock
Oscillator
Output
Signal Direction Description
Bidirectional
Input, Active Low Modem status signal to the UART.
Bidirectional
Input, Active Low Modem status signal to the UART.
Bidirectional
Output
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
This signal is multiplexed with PD5.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
This signal is multiplexed with PD6.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
This signal is multiplexed with PD7.
Power Supply.
Ground.
Loop Filter pin for the Analog PLL.
Ground for Analog PLL.
This pin is the output of the onboard
crystal oscillator. When used, a crystal
must be connected between X
X
OUT
.
Product Specification
Architectural Overview
IN
and
13