EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 203

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

Table 108. UART Scratch Pad Registers
PS019215-0910
Bit 
Position
3
DDCD
2
TERI
1
DDSR
0
DCTS
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit 
Position
[7:0]
SPR
Value
00h–FFh
UART Scratch Pad Register
The UARTx_SPR register is used by the system as a general-purpose Read/Write register.
See
Value
0–1
0–1
0–1
0–1
Table
Description
UART scratch pad register is available for use as a general-
purpose Read/Write register. In multi-drop 9 bit mode, this
register is used to store the address value.
Description
Delta Status Change of DCD.
This bit is set to 1 whenever the DCDx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Trailing Edge Change on RI.
This bit is set to 1 whenever a falling edge is detected on the
RIx pin. This bit is reset to 0 when the UARTx_MSR register is
read.
Delta Status Change of DSR.
This bit is set to 1 whenever the DSRx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Delta Status Change of CTS.
This bit is set to 1 whenever the CTSx pin changes state.
This bit is reset to 0 when the UARTx_MSRs register is read.
R/W
108.
7
0
R/W
6
0
R/W
5
0
(UART0_SPR = 00C7h, UART1_SPR = 00D7h)
R/W
4
0
R/W
3
0
Universal Asynchronous Receiver/Transmitter
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
eZ80F91 MCU
194