EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 125

• Manufacturer Part Number: EZ80F91AZ050EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91AZ050EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3867; EZ80F91AZ050EG

PS019215-0910
Watchdog Timer Operation
Enabling and Disabling the Watchdog Timer
The WDT is disabled on a RESET. To enable the WDT, the application program must set
WDT_EN, which is bit 7 of the WDT_CTL register. After WDT_EN is set, no Writes are
allowed to the WDT_CTL register. When enabled, the WDT cannot be disabled except by
a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT. The WDT time-out period is
defined by the WDT_PERIOD WDT_CTL[1:0] field and WDT_CLK WDT_CTL[3:2]
field of the Watchdog Timer control register (WDT_CTL = 0093h). The approximate
time-out period and corresponding clock cycles for three different WDT clock sources are
listed in
The WDT time-out period divider is set to one of the four available settings for the
selected frequency of the WDT clock source. Basing the divider settings on the clock
source values provides a time-out range from few seconds to few msecs, regardless of the
frequency setting.
Table 47. WDT Approximate Time-Out Delays for Possible Clock Sources
RESET or NMI Generation
A WDT time-out causes a RESET or sends a NMI signal to the CPU. The default opera-
tion is for the WDT to cause a RESET.
If the NMI_OUT bit in the WDT_CTL register is set to 0, then on a WDT time-out, the
RST_FLAG bit in the WDT_CTL register is set to 1. The RST_FLAG bit is polled by the
CPU to determine the source of the RESET event.
WDT_CLK[
3:2]
WDT_PERI
OD[1:0]
00
01
10
11
Table
Divider Timeout
47.
50 MHz system
2
2
2
2
27
25
22
18
clock
00
83.9 ms
5.2 ms
2.68 s
0.67 s
Divider
32.768 kHz RTC
2
2
2
2
17
14
11
7
clock
01
Timeout Divider Timeout Divider Timeout
62.5 ms
3.9 ms
4.00 s
0.5 s
oscillator (~10
2
2
2
2
Internal RC
15
13
9
5
kHz)
10
51.2 ms
3.2 ms
3.28 s
0.82 s
Product Specification
eZ80F91 MCU
-
-
-
-
Reserved
Watchdog Timer
11
-
-
-
-
116