DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 165

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.2.2
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3
BCRA controls channel A PC breaks.
Bit
7
6
5
4
3
2
1
Bit Name
CMFA
CDA
BAMRA2
BAMRA1
BAMRA0
CSELA1
CSELA0
Break Address Register B (BARB)
Break Control Register A (BCRA)
Initial
Value
0
0
0
0
0
0
0
R/W
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
1
Description
Condition Match Flag A
[Setting condition]
When a condition set for channel A is satisfied
[Clearing condition]
When 0 is written to CMFA after reading*
CPU Cycle/DTC Cycle Select A
Selects the channel A break condition bus master.
0: CPU
1: CPU or DTC
Break Address Mask Register A2 to A0
These bits specify which bits of the break address set in
BARA are to be unmasked.
000: BAA23 to BAA0 (All bits are unmasked)
001: BAA23 to BAA1 (Lowest bit is masked)
010: BAA23 to BAA2 (Lower 2 bits are masked)
011: BAA23 to BAA3 (Lower 3 bits are masked)
100: BAA23 to BAA4 (Lower 4 bits are masked)
101: BAA23 to BAA8 (Lower 8 bits are masked)
110: BAA23 to BAA12 (Lower 12 bits are masked)
111: BAA23 to BAA16 (Lower 16 bits are masked)
Break Condition Select
These bits select the break condition of channel A.
00: Instruction fetch is used as the break condition.
01: Data read cycle is used as the break condition.
10: Data write cycle is used as the break condition.
11: Data read/write cycle is used as the break condition.
Rev. 6.00 Sep. 24, 2009 Page 117 of 928
Section 6 PC Break Controller (PBC)
2
REJ09B0099-0600
CMFA = 1