DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 722

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory
3. Initialization of programming/erasing
4. Programming/erasing execution
Rev. 6.00 Sep. 24, 2009 Page 674 of 928
REJ09B0099-0600
working from download to completion of programming/erasing, must be executed in the space
other than the flash memory to be programmed/erased (for example, on-chip RAM).
Since the result of download is returned to the programming/erasing interface parameter,
whether the normal download is executed or not can be confirmed.
The operating frequency and user branch are set before execution of programming/erasing.
The user branch area should be outside programming-prohibited areas such as user MAT area
during programming process or on-chip program area. This setting is performed by using the
programming/erasing interface parameter.
To execute programming/erasing, it is necessary to enter user program mode by setting
FLSHE bit in SYSCR2 to 1.
The program data/programming destination address is specified in 128-byte units when
programming.
The block to be erased is specified in erase-block units when erasing.
These specifications are set by using the programming/erasing interface parameter and the on-
chip program is initiated. The on-chip program is executed by using the JSR or BSR
instruction and performing the subroutine call of the specified address in the on-chip RAM.
The execution result is returned to the programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory. It is,
however, impossible to download at the same time the erasing program and the programming
program. Therefore, execute the above procedures of 1 to 4 in the order of erasing first and
programming next.
All interrupts are prohibited during programming and erasing. Interrupts must be masked
within the user system.
Access in the flash memory space during programming/erasing is not guaranteed. Accordingly,
when the interrupt vector or the interrupt handler is in the flash memory, interrupt processing
is not guaranteed. When NMI interrupt is inevitable during overprogramming/erasing system
such as in system error processing, set FVACR and FVADR to set the interrupt vector and the
interrupt processing routine in the on-chip RAM or the external space.