DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 185

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Bus Controller
Area 0: Area 0 includes on-chip ROM, and in ROM-enabled extended mode, space excluding on-
chip ROM is external address space.
When external address space of area 0 is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 to 6: In external extended mode, all of areas 1 to 6 are external address spaces. When
external address spaces of areas 1 to 6 are accessed, the CS1 to CS6 pin signals can be output
respectively. Only the basic bus interface can be used for areas 1 to 6.
Area 7: Area 7 includes on-chip RAM and internal l/O registers. In external extended mode, the
space excluding on-chip RAM and internal l/O registers, is external address space. The on-chip
RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external address space.
When external address space of area 7 is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for area 7.
7.4.4
Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) to areas 0 to 7, and these signals are driven
low respectively when the corresponding external address space area is accessed. Figure 7.3 shows
an example of CSn (n = 0 to 7) signal output timing. Enabling or disabling of the CSn signal is
performed by setting the data direction register (DDR) for the port corresponding to the particular
CSn pin.
In ROM-enabled extended mode, pins CS0 to CS7 are all placed in the input state after a power-
on reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS7.
For details, see section 9, I/O Ports.
Rev. 6.00 Sep. 24, 2009 Page 137 of 928
REJ09B0099-0600