DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 944

IC H8S/2552 MCU FLASH 176-LFBGA

DF2552BR26DV

Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2552BR26DV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2552BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 24 Electrical Characteristics
Notes: 1. The regular specifications are supported in the H8S/2506 Group only.
Rev. 6.00 Sep. 24, 2009 Page 896 of 928
REJ09B0099-0600
Item
SCI*
A/D
converter
HCAN*
3
2
2. (For H8S/2556 Group) The HCAN input signal is asynchronous, but checked as if it has
3. The P35/SCK1/SCK4 and P34 pins are driven high by NMOS. To output high, the pull-
Input clock cycle Asynchronous t
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
Trigger input setup time
Transmit data delay time
Transmit data setup time
Transmit data hold time
been changed at the φ clock rise (two clock intervals) shown in figure 24.24. The HCAN
output signal is asynchronous, but it changes at the φ clock rise (two clock intervals)
shown in figure 24.24.
up resistor should be connected externally.
Synchronous
Symbol Min.
t
t
t
t
t
t
t
t
t
t
Scyc
SCKW
SCKr
SCKf
TXD
RXS
RXH
TRGS
HTXD
HRXS
HRXH
4
6
0.4
38
38
28
Condition A
Max.
0.6
1.5
1.5
50
Min.
4
6
0.4
50
50
30
30
30
Condition B
Max.
0.6
1.5
1.5
50
50
Unit
t
t
t
ns
ns
ns
ns
ns
ns
ns
cyc
Scyc
cyc
Test
Conditions
Figure 24.21
Figure 24.22
Figure 24.23
Figure 24.24

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