DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 26

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 RAM .................................................................................................. 663
Section 20 Flash Memory.................................................................................... 665
20.1 Features.............................................................................................................................. 665
20.2 Pin Configuration............................................................................................................... 675
20.3 Register Descriptions......................................................................................................... 676
20.4 On-Board Programming Mode .......................................................................................... 699
20.5 Protection........................................................................................................................... 726
20.6 Flash Memory Emulation in RAM .................................................................................... 729
20.7 Switching between User MAT and User Boot MAT......................................................... 732
20.8 Usage Notes ....................................................................................................................... 733
20.9 Programmer Mode ............................................................................................................. 734
Rev. 6.00 Sep. 24, 2009 Page xxiv of xlvi
REJ09B0099-0600
18.8.9 Usage of Bit Change Instructions ......................................................................... 658
18.8.10 HCAN TXCR Operation ...................................................................................... 658
18.8.11 HCAN Transmit Procedure .................................................................................. 659
18.8.12 Canceling HCAN Software Reset or HCAN Sleep Mode .................................... 661
18.8.13 Accessing Mailboxes in HCAN Sleep Mode........................................................ 661
20.1.1 Block Diagram...................................................................................................... 667
20.1.2 Operating Mode .................................................................................................... 668
20.1.3 Mode Comparison ................................................................................................ 670
20.1.4 Flash MAT Configuration .................................................................................... 671
20.1.5 Block Division ...................................................................................................... 672
20.1.6 Programming/Erasing Interface ............................................................................ 673
20.3.1 Programming/Erasing Interface Register.............................................................. 677
20.3.2 Programming/Erasing Interface Parameter........................................................... 684
20.3.3 RAM Emulation Register (RAMER).................................................................... 696
20.3.4 Flash Vector Address Control Register (FVACR)................................................ 697
20.3.5 Flash Vector Address Data Register (FVADR) .................................................... 698
20.4.1 Boot Mode ............................................................................................................ 699
20.4.2 User Program Mode.............................................................................................. 703
20.4.3 User Boot Mode.................................................................................................... 714
20.4.4 Procedure Program and Storable Area for Programming Data............................. 718
20.5.1 Hardware Protection ............................................................................................. 726
20.5.2 Software Protection .............................................................................................. 727
20.5.3 Error Protection .................................................................................................... 727
20.9.1 Pin Arrangement of Socket Adapter ..................................................................... 734
20.9.2 Programmer Mode Operation ............................................................................... 736
20.9.3 Memory-Read Mode............................................................................................. 737
20.9.4 Auto-Program Mode ............................................................................................. 738