DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 643

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4)
Figure 17.10 shows an example in which a receive error occurs because the receive preparation
cannot be completed (the RxRDY flag is not cleared) until the control field is received in
broadcast reception after the slave reception while the DEE bit is set to 1.
Note: The same as the case in which the RE bit is not set before the control field reception.
RE, DEE
IERSR
IECTR
IEFLG
IEFLG
RxRDY
IEMA1
IEMA2
MRQ
CMX
SRQ
RxS
RxE
RSS
SRE
RxF
When an Error Occurs in Broadcast Reception (DEE = 1)
Slave reception
Figure 17.10 Error Occurrence in the Broadcast Reception (DEE = 1)
H: Header, MA: Master address field, SA: Slave address field,
CF: Control field, LF: Message length field, D1, D2,..., Dn-1, Dn: Data field
Dn
Broadcast reception is performed while the DEE bit is set to 1.
H
MA
Set the RxE flag and the master unit address in IEAR1 and IEAR2.
SA
CF
The RxRDY flag has not been cleared when the control field is received.
Broadcast reception
LF
Lower 4 bits of the master address
Upper 8 bits of the master address
D1
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
D2
Rev. 6.00 Sep. 24, 2009 Page 595 of 928
Dn-1
Dn
REJ09B0099-0600