DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 963

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
9.1.4
•
9.13.4
•
12.3.1 Timer Counter
(TCNT)
12.6.7 Initialization of
TCNT by the TME Bit
13.3.7 Serial Status
Register (SSR)
•
P17/TIOCB2/TCLKD
PF2/WAIT
Normal Serial
Communication
Interface Mode (When
SMIF in SCMR Is 0)
Pin Functions
Pin Functions
Main Revisions for This Edition
Page
201
254
380
393
410
Revision (See Manual for Details)
Table amended
Table amended
Description added
TCNT is initialized to H'00 when the TME bit in TCSR is
cleared to 0.
To initialize TCNT to H’00 during timer operation, write a value
of H'00 directly to TCNT. For details, see 12.6.7, Initialization
of TCNT by the TME Bit.
Newly added
Table amended and note added
TPU Channel 2 Setting*
P17DDR
Pin function
Operating mode
WAITE
PF2DDR
Pin function
Bit
7
6
TDRE
RDRF
Bit Name
Initial
Value
1
0
1
PF2 input
0
TIOCB2 output
R/W
R/(W)*
R/(W)*
Output
0
1
1
PF2 output
Rev. 6.00 Sep. 24, 2009 Page 915 of 928
Mode 6
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF
flag is still set to 1, an overrun error will occur and the
receive data will be lost.
0
1
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data
can be written to TDR
When 0 is written to TDRE after reading TDRE = 1*
When the DTC*
request and writes data to TDR
When serial reception ends normally and receive data
is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1*
When the DTC*
transfers data from RDR
TCLKD input*
P17 input
WAIT input
⎯
Input or Initial Value
1
2
2
TIOCB2 input*
is activated by a TXI interrupt
is activated by an RXI interrupt and
3
PF2 input
REJ09B0099-0600
P17 output
2
0
1
Mode 7
⎯
PF2 output
1
3
3