DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 434

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Watchdog Timer (WDT)
12.4
12.4.1
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1.
Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00)
before overflows occurs. Thus, TCNT does not overflow while the system is operating normally.
When the WDT is used as a watchdog timer and the RSTE bit in RSTCSR of WDT_0 is set to 1,
and if TCNT overflows without being rewritten because of a system malfunction or other error, an
internal reset signal for this LSI is output for 518 system clocks.
When the RST/NMI bit in TCSR of WDT_1 is set to 1, and if TCNT overflows, the internal reset
signal is output for 516 system clocks. When the RST/ NMI bit is cleared to 0, if TCNT
overflows, an NMI interrupt request is generated (for 515 or 516 system clocks when the clock
source is set to φ
An internal reset request from the watchdog timer and a reset input from the RES pin are both
treated as having the same vector. If a WDT internal reset request and the RES pin reset occur at
the same time, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
both treated as having the same vector. So, avoid handling an NMI interrupt request from the
watchdog timer and an interrupt request from the NMI pin at the same time.
Rev. 6.00 Sep. 24, 2009 Page 386 of 928
REJ09B0099-0600
Operation
Watchdog Timer Mode
SUB
(PSS = 1)).