DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 757

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(j) FKEY must be set to H'5A and the user MAT must be prepared for programming.
(k) The parameter which is required for programming is set.
(l) Programming
The NMI interrupts must be masked within the user system.
The interrupts that are held must be executed in the user branch destination or after all program
processing. When the interrupt processing is executed in the user branch destination, prohibit
the interrupt in the CCR register of the CPU after the process completes.
When the movement of bus mastership to other than the CPU, error protection state is entered.
Therefore, prevent other than the CPU from getting bus, as is the case with interrupt
prohibition.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register ER1. The start address of the program data area (FMPDR) is set to general register
ER0.
⎯ Example of the FMPAR setting
⎯ Example of the FMPDR setting
There is an entry point of the programming program in the area from the start address specified
by FTDAR + 16 bytes of the on-chip RAM. The subroutine is called and programming is
executed by using the following steps.
MOV.L
JSR
NOP
⎯ The general registers other than R0L are held in the programming program.
⎯ R0L is a return value of the FPFR parameter.
FMPAR specifies the programming destination address. When an address other than one in
the user MAT area is specified, even if the programming program is executed,
programming is not executed and an error is returned to the return value parameter FPFR.
Since the unit is 128 bytes, the lower eight bits (A7 to A0) must be H'00 or H'80 as the
boundary of 128 bytes.
When the storage destination of the program data is flash memory, even if the program
execution routine is executed, programming is not executed and an error is returned to the
FPFR parameter. In this case, the program data must be transferred to the on-chip RAM
and then programming must be executed.
#DLTOP+16,ER2
@ER2
; Set entry address to ER2
; Call programming routine
Rev. 6.00 Sep. 24, 2009 Page 709 of 928
Section 20 Flash Memory
REJ09B0099-0600