DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 597

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(7)
The parity bit is used to confirm that transfer data has no error.
The parity bit is added to respective data of the master address, slave address, control, message
length, and data bits.
The even parity is used. When the number of one bits in data is odd, the parity bit is 1. When the
number of one bits in data is even, the parity bit is 0.
(8)
In normal communications (a single unit to a single unit communications), the acknowledge bit is
added to the following position in order to confirm that data is correctly accepted.
• At the end of the slave address field
• At the end of the control field
• At the end of the message length field
• At the end of the data field
The acknowledge bit is defined below.
• 0: indicates that the transfer data is acknowledged. (ACK)
• 1: indicates that the transfer data is not acknowledged. (NAK)
Note that the acknowledge bit is ignored in the case of broadcast communications.
(a) Acknowledge bit at the End of the Slave Address Field
The master unit reads the parity bit output from the slave unit, and checks the parity. If the
parity is not correct, or the receive buffer is not empty, the master unit rejects acceptance of the
data, and does not return the acknowledgement. The master unit reads the same data repeatedly
if the number of data does not exceed the maximum number of transfer bytes in one frame. If
the parity is correct and the receive buffer is empty, the master unit accepts data and returns the
acknowledgement. The master unit reads in the subsequent data if the number of data does not
exceed the maximum number of transfer bytes in one frame.
The acknowledge bit at the end of the slave address field becomes NAK in the following cases
and transfer is stopped.
⎯ When the parity of the master address or slave address bits is incorrect
⎯ When a timing error (an error in bit format) occurs
⎯ When there is no slave unit
Parity bit
Acknowledge bit
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Rev. 6.00 Sep. 24, 2009 Page 549 of 928
REJ09B0099-0600