DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 213

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.10
This LSI has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DTC, which perform read/write operations when they
have possession of the bus. Each bus master requests the bus mastership by means of a bus request
signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by
means of a bus mastership request acknowledge signal. The selected bus master then takes
possession of the bus mastership and begins its operation.
7.10.1
The bus arbiter detects the bus masters’ bus mastership request signals, and if the bus mastership
is requested, sends a bus mastership request acknowledge signal to the bus master. If there are bus
mastership requests from more than one bus master, the bus mastership request acknowledge
signal is sent to the one with the highest priority. When a bus master receives the bus mastership
request acknowledge signal, it takes possession of the bus until that signal is canceled.
The order of priority of the bus masters is as follows:
An internal bus access by an internal bus master, and external bus mastership release, can be
executed in parallel.
In the event of simultaneous external bus mastership release request, and internal bus master
external access request generation, the order of priority is as follows:
7.10.2
Even if a bus mastership request is received from a bus master with a higher priority than that of
the bus master that has acquired the bus and is currently operating, the bus mastership is not
necessarily transferred immediately. There are specific times at which each bus master can
relinquish the bus mastership.
CPU: The CPU is the lowest-priority bus master, and if a bus mastership request is received from
the DTC, the bus arbiter transfers the bus mastership to the bus master that issued the request. The
timing for transfer of the bus mastership is as follows:
(High) DTC > CPU (Low)
(High) External bus mastership release > Internal bus master external access (Low)
Bus Arbitration
Operation
Bus Mastership Transfer Timing
Rev. 6.00 Sep. 24, 2009 Page 165 of 928
Section 7 Bus Controller
REJ09B0099-0600