DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 22

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
14.1 Features.............................................................................................................................. 475
14.2 Input/Output Pins............................................................................................................... 478
14.3 Register Descriptions......................................................................................................... 479
14.4 Operation ........................................................................................................................... 492
14.5 Interrupt Request................................................................................................................ 509
14.6 Bit Synchronous Circuit..................................................................................................... 510
14.7 Note on Usage.................................................................................................................... 511
Section 15 A/D Converter ................................................................................... 513
15.1 Features.............................................................................................................................. 513
15.2 Input/Output Pins............................................................................................................... 515
15.3 Register Descriptions......................................................................................................... 516
Rev. 6.00 Sep. 24, 2009 Page xx of xlvi
REJ09B0099-0600
14.3.1 I
14.3.2 I
14.3.3 I
14.3.4 I
14.3.5 I
14.3.6 Slave Address Register (SAR).............................................................................. 490
14.3.7 I
14.3.8 I
14.3.9 I
14.4.1 I
14.4.2 Master Transmit Operation................................................................................... 493
14.4.3 Master Receive Operation .................................................................................... 495
14.4.4 Slave Transmit Operation ..................................................................................... 497
14.4.5 Slave Receive Operation....................................................................................... 499
14.4.6 Clocked Synchronous Serial Format .................................................................... 501
14.4.7 Noise Canceler...................................................................................................... 503
14.4.8 Example of Use..................................................................................................... 504
14.7.1 Setting Module Stop Mode ................................................................................... 511
14.7.2 Issuance of Stop and Repeated Start Conditions................................................... 511
14.7.3 WAIT Bit in I
14.7.4 Usage Note on Master Receive Mode................................................................... 512
14.7.5 Restriction on Setting of Transfer Rate in Use of Multi-Master........................... 512
14.7.6 Restriction on Use of Bit Manipulation Instructions to Set MST and TRS when
15.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 516
15.3.2 A/D Control/Status Register (ADCSR) ................................................................ 517
2
Multi-Master Is Used ............................................................................................ 512
C Bus Interface 2 (IIC2).................................................................. 475
2
2
2
2
2
2
2
2
2
C Bus Control Register 1 (ICCR1)..................................................................... 479
C Bus Control Register 2 (ICCR2)..................................................................... 482
C Bus Mode Register (ICMR)............................................................................ 483
C Bus Interrupt Enable Register (ICIER)........................................................... 486
C Bus Status Register (ICSR)............................................................................. 488
C Bus Transmit Data Register (ICDRT) ............................................................ 491
C Bus Receive Data Register (ICDRR).............................................................. 491
C Bus Shift Register (ICDRS)............................................................................ 491
C Bus Format...................................................................................................... 492
2
C Bus Mode Register (ICMR) ...................................................... 511