DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 428

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Watchdog Timer (WDT)
12.3
The WDT has the following three registers. To prevent accidental overwriting, TCSR and TCNT
have to be written to by a different method from normal registers. For details, see section 12.6.1,
Notes on Register Access. For detailed description on the system control register, see section
3.2.2, System Control Register (SYSCR). For details on the pin function control register, see
section 7.3.6, Pin Function Control Register (PFCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
12.3.1
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
TCSR is cleared to 0.
To initialize TCNT to H’00 during timer operation, write a value of H'00 directly to TCNT. For
details, see 12.6.7, Initialization of TCNT by the TME Bit.
12.3.2
TCSR functions include selecting the clock source to be input to TCNT and the timer mode.
• TCSR_0
Rev. 6.00 Sep. 24, 2009 Page 380 of 928
REJ09B0099-0600
Bit
7
Bit Name
OVF
Register Descriptions
Timer Counter (TCNT)
Timer Control/Status Register
0
Initial
Value
R/W
R/(W)*
1
Description
Overflow Flag
Indicates that TCNT has overflowed. Only a 0 can be
written to this bit, to clear the flag.
[Setting condition]
When TCNT overflows (changes from H'FF to H'00).
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
Cleared by reading TCSR*
to OVF
2
when OVF = 1, then writing 0